18-bit universal bus drivers with 3-state outputs.
* VCC = 2.3 V to 3.6 V
* Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
* Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
* High out.
Data flow from A to Y is controlled by the output enable (OE ). The device operates in the transparent mode when LE is high. The A data is latched if CLK is held at a high or low logic level. If LE is low, the A bus data is stored in the latch flip f.
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